Jan Vardaman, President, TechSearch International: "Challenges and Opportunities for Materials in Backend Processing and Assembly"
Packaging challenges: new ILDs and pad stacks introducing stress issues, worse with Pb-free bumps and ELK; 16% of all IC shipments will be Flip-Chip & WLP; assembly price pressure driving Cu replacement of Au; 2010 capex spending was 2.7X that of 2009, 300mm WLP a leading cause; Flip Chip will grow 15% through 2014; shift is towards Cu pillar; this will drive growth in plating chemistries, underfills, substrates; WLP growth will be 12.5% through 2014, driving growth in dielectrics for reliability improvement, looking for low cure temp, lower k, high breakdown strengths; Fan-out WLP packages will emerge as new technology; 300mm WLP will see capacity shortage near term; WLP highest I/O count is 309 by Fujitsu.
3D & High Density packaging trends: smart phones universally featuring stacks; tablets also making heavy use of stacks, WLP, package-on-package (PoP); PoP will triple by 2014; expecting TSV to shift out as high volume production technology from 2011 to 2012; TSVs /3D IC is expected to reach major market size (>3M 300mm wpy) in 2015; TSV challenges are via filling, improved chemistries; joining processes like direct bonding/Cu pillar/etc.; thinning & handling, singulation, inspection & FA; a long laundry list of issues still remain to be resolved for TSV, opening door for alternatives such as stacked silicon interconnect (Xilinx), Chip-on-Chip, PoP, etc.
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