Paolo Gargini, Chairman, ITRS; Intel Fellow; Director, Technology Strategy, Intel Corporation, kicked of the first day of the combined ISS/SMC conference by discussing the current challenges that face Intel and by extension the Semiconductor Industry as a whole.  He prefaced the talk with a brief history of the development of current day CMOS technology, emphasizing the importance of the new materials and scaling for improved mobilities.  The next phase of introducing III-V transistor devices is where Intel would like the industry to work to accelerate the development cycle to something less than the 15 year time to market that has been the historical norm.  Looking forward, the next, perhaps even more challenging technology will involve introducing Graphene devices.  The  "New Devices" will utilize new physics outside of the "MOS Box".  Intel has been working with various industry entities to explore these new technologies and went into some depth on their Intel's current interest in Tunnel FET devices.  The challenge in conclusion was to reduce the incubation time as each of these new technologies is developed.